IOE Helper
Programs
Objective
To introduce basic principles of digital logic design, its implementation and applications
Syllabus
Introduction
Definitions for Digital Signals
Digital Waveforms
Digital Logic
Moving and Storing Digital Information
Digital Operations
Digital Computer
Digital Integrated Circuits
Digital IC Signal Levels
Clock wave form
Coding
ASCII Code
BCD
The Excess – 3 Code
The Gray Code
Digital Logic
The Basic Gates – NOT, OR, AND
Universal Logic Gates – NOR, NAND
AND-OR-INVERT Gates
Positive and Negative Logic
Introduction to HDL
Combinational Logic Circuits
Boolean Laws and Theorems
Sum-of-Products Method
Truth Table to Karnaugh Map
Pairs, Quads, and Octets
Karnaugh Simplifications
Don’t Care Conditions
Product-of-Sums Method
Product-of-Sums Simplification
Hazards and Hazard Covers
HDL Implementation Models
Data Processing Circuits
Multiplexetures
Demultiplexetures
Decoder
BCD-to-Decimal Decoders
Seven-Segment Decoders
Encoder
Exclusive-OR Gates
Parity Generators and Checkers
Magnitude Comparator
Read-Only Memory
Programmable Array Logic
Programmable Logic Arrays
Troubleshooting with a Logic Probe
HDL Implementation of Data Processing Circuits
Arithmetic Circuits
Binary Addition
Binary Subtraction
Unsigned Binary Numbers
Sign-Magnitude Numbers
2’s Complement Representation
2’s Complement Arithmetic
Arithmetic Building Blocks
The Adder-Subtracter
Fast Adder
Arithmetic Logic Unit
Binary Multiplication and Division
Arithmetic Circuits Using HDL
Flip Flops
RS Flip-Flops
Gated Flip-Flops
Edge-Triggered RS Flip-Flops
Egde Triggered D Flip-Flops
Egde Triggered J K Flip-Flops
Flip-Flop Timing
J K Mater- Slave Flip-Flops
Switch Contacts Bounds Circuits
Varius Representation of Flip-Flops
Analysis of Sequencial Circuits
Registers
Types of Registers
Serial In – Serial Out
Serial In – Parallel Out
Parallel In – Serial Out
Parallel In – Parallel Out
Applications of Shift Registers
Counters
Asynchronous Counters
Decoding Gates
Synchronous Counters
Changing the Counter Modulus
Decade Counters
Presettable Counters
Counter Design as a Synthesis Problem
A Digital Clock
Sequential Machines
Synchronous machines
Clock driven models and state diagrams
Transition tables, Redundant states
Binary assignment
Use of flip-flops in realizing the models
Asynchronous machines
Hazards in asynchronous system and use of redundant branch
Allowable transitions
Flow tables and merger diagrams
Excitation maps and realization of the models
Digital Integrate Circuits
Switching Circuits
7400 TTL
TTL parameters
TTL Overvew
Open Collecter Gates
Three-state TTL Devices
External Drive for TTL Lods
TTL Driving External Loads
74C00 CMOS
CMOS Characteristics
TTL- to –CMOS Interface
CMOS- to- TTL Interface
Applications
Multiplexing Displays
Frequency Counters
Time Measurement