Computer Organization and Architecture

Syllabus

1. Introduction (5 hours)
   1. Organization and architecture
   2. Structure of a computer, single processor, multi-core computer
   3. Performance assessment: clock speed and instruction per second; instruction execution rate (CPI, MIPS rate, MFLOPS rate, arithmetic mean, harmonic mean, speed metric, geometric mean, rate metric, Amdahl's law, speed up)
   4. Computer function: instruction fetch and execute, instruction cycle state diagram
   5. Computer component, interconnection structure, bus interconnection, PCI
   6. RISC architecture, overlapped register windows, Berkeley RISC
2. Central Processing Unit (CPU) (7 hours)
   1. Processor bus organization
   2. Processor register organization: control word, examples of microoperations
   3. Stack organization: register stack, memory stack, reverse polish notation, evaluation of arithmetic expressions
   4. Instruction formats: CPU organization, zero and more address instruction formats
   5. Addressing modes: types, examples, strengths and weaknesses
   6. Instruction set: data transfer, data manipulation (arithmetic, logical and shift), program control
   7. Status bit conditions
   8. Interrupt: definition, types, processing and ISR
3. Control Unit (5 hours)
   1. Hardwired control unit
   2. Microprogrammed control unit
   3. Microinstructions, control memory organization, Wilkes control
   4. Microinstruction sequencing: design considerations, sequencing techniques, address generation, microinstruction encoding
   5. Application of microprogramming
   6. Microinstruction execution
4. Memory System (7 hours)
   1. Characteristics of memory system
   2. Memory classification and hierarchy
   3. Semiconductor memory and its types, read only memory, read/write memory
   4. RAM modules and interfaces: DDR, DIMM and SODIMM
   5. Cache memory: cache principles, elements of cache design (cache size, mapping function, replacement algorithms, write policy, block size, single and multi-level caches, unified versus split cache)
   6. External memory: magnetic disk, RAID (level 1 to 5), optical memory, magnetic tape, SSD
5. Computer Arithmetic (8 hours)
   1. ALU (arithmetic and logic unit)
   2. Integer representation: sign-magnitude, two's complement, converting between different bit lengths, fixed-point representation
   3. Integer arithmetic: addition and subtraction, multiplication, division algorithms
   4. Floating-point arithmetic: representation (principles, IEEE standard), addition and subtraction, multiplication, division algorithms
6. Pipelining and Vector Processing (4 hours)
   1. Pipelining and its importance
   2. Instruction and arithmetic pipelining
   3. Pipelining hazards: data, structural and control hazards
   4. RISC pipeline
   5. Parallel processing
   6. Vector processing: vector operations, matrix multiplication, memory interleaving, superscalar processors, supercomputers
   7. Array processors: attached array processor and SIMD array processor
7. Input/Output (5 hours)
   1. External devices
   2. I/O modules: module function, module structure
   3. Programmed I/O, I/O commands, I/O instructions, flowchart
   4. Interrupt driven I/O, interrupt processing and flowchart
   5. Direct memory access (DMA): drawbacks of programmed and interrupt-driven I/O, DMA function, typical DMA block diagram and configurations
   6. I/O channels and processors: evolution of the I/O function, characteristics of I/O channels
   7. The external interface: types of interfaces, point-to-point and multiple configurations, SCSI
8. Multiprocessor System (4 hours)
   1. Multiprocessor computers and their characteristics
   2. Multi-core computers and their architecture
   3. Interconnection structure: time-shared common bus, multiport memory, crossbar switch, multistage switching network and hypercube system
   4. Interprocessor arbitration
   5. Interprocessor communication and synchronization

Practicals

1. Addition and subtraction algorithm
2. Multiplication algorithm
3. Division algorithm
4. Cache mapping techniques
5. ALU implementation
6. Vector processing implementation